发明名称 Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material
摘要 A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.
申请公布号 US9425193(B2) 申请公布日期 2016.08.23
申请号 US201214129630 申请日期 2012.06.22
申请人 Pragmatic Printing Ltd 发明人 Price Richard;White Scott
分类号 H01L21/12;H01L27/12;H01L29/66;H01L29/786;H01L21/768;H01L27/088;H01L21/027 主分类号 H01L21/12
代理机构 Myers Bigel & Sibley, P.A. 代理人 Myers Bigel & Sibley, P.A.
主权项 1. A method of manufacturing a transistor, the method comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of electrically conductive material, said first portion separating a second portion of the region of electrically conductive material from a third portion of the region of electrically conductive material; removing resist material located under said depression so as to form a first window, through said covering of resist material, exposing said first portion of the region of electrically conductive material; removing said first portion of the region of electrically conductive material to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion of the region of electrically conductive material to the third portion of the region of electrically conductive material; forming a layer of dielectric material over the exposed connecting portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the region of electrically conductive material, wherein said second and third portions of the region of electrically conductive material provide a source terminal and a drain terminal, respectively, wherein the layer of electrically conductive material provides a gate terminal to which a potential may be applied to control a conductivity of the connecting portion of the region of semiconductive material connecting the second and third portions of the region of electrically conductive material, wherein forming said depression in a surface of the covering of resist material comprises forming said depression by imprinting using an imprinting tool, wherein the imprinting tool comprises a plurality of imprint features each raised a respective height above a base surface of the imprinting tool, wherein the plurality of imprint features comprises a first imprint feature raised a first height above the base surface, and wherein forming said depression comprises forming the depression with the first imprint feature, such that the depression initially has a depth substantially equal to the first height, and wherein the plurality of imprint features comprises a second imprint feature raised a second height above the base surface, the second height being greater than the first height, and the second imprint feature being arranged to define a perimeter of the transistor, and the method further comprising using the second imprint feature to form a second depression in the surface of the covering of resist material, said second depression extending around the first, second, and third portions of said region of electrically conductive material.
地址 Sedgefield GB