Memory program upon system failure

摘要

A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.

主权项

1. A system comprising:
a timer device integrated on a host device; a buffer, integrated on an another device, configured to receive debug data representative of one or more probed nodes in the system; a register, integrated on the another device, configured to receive memory address information; and a memory device, integrated on the another device, configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero, wherein the buffer is configured to transfer the debug data to the memory device in response to a system failure program command issued on a dedicated line.