发明名称 METHODS FOR CELL PHASING AND PLACEMENT IN DYNAMIC ARRAY ARCHITECTURE AND IMPLEMENTATION OF THE SAME
摘要 <p>A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.</p>
申请公布号 KR20110050638(A) 申请公布日期 2011.05.16
申请号 KR20117003546 申请日期 2009.07.02
申请人 TELA INNOVATIONS, INC. 发明人 QUANDT JONATHAN R.;BECKER SCOTT T.;GANDHI DHRUMIL
分类号 H01L27/02;G06F17/50;H01L27/118 主分类号 H01L27/02
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