| 发明名称 |
Voltage optimization circuit and managing voltage margins of an integrated circuit |
| 摘要 |
A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators. |
| 申请公布号 |
US9389622(B2) |
申请公布日期 |
2016.07.12 |
| 申请号 |
US201514876332 |
申请日期 |
2015.10.06 |
| 申请人 |
Nvidia Corporation |
发明人 |
Smith Brian L.;Felix Stephen;Guss Jesse Max;Raja Tezaswi |
| 分类号 |
G05F1/10;G05F3/02;G05F1/46 |
主分类号 |
G05F1/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A voltage margin controller located in a voltage domain and comprising:
monitoring branches including circuit function indicators configured to indicate whether circuitry in said voltage domain could operate at corresponding candidate reduced voltage levels; and a voltage margin adjuster coupled to said monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of said voltage domain based upon an operating number of said circuit function indicators, wherein said operating number is a number of consecutive passing function indicators directly below an operating voltage provided by said voltage regulator for said voltage domain. |
| 地址 |
Santa Clara CA US |
