| 摘要 |
A memory cell of an SRAM has a full CMOS cell structure having successively aligned three wells of different conductivity types, and includes first and second contact holes extending from positions on first and second gates to positions above an impurity region of a predetermined MOS transistor, and formed in a self-aligned fashion with respect to the first and second gates, and first and second local interconnections formed in the contact holes, respectively.
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