发明名称 |
Microcomputer |
摘要 |
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3 . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
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申请公布号 |
US2006224859(A1) |
申请公布日期 |
2006.10.05 |
申请号 |
US20060354622 |
申请日期 |
2006.02.14 |
申请人 |
OHSUGA HIROSHI;KIUCHI ATSUSHI;HASEGAWA HIRONOBU;BAJI TORU;NOGUCHI KOKI;AKAO YASUSHI;BABA SHIRO |
发明人 |
OHSUGA HIROSHI;KIUCHI ATSUSHI;HASEGAWA HIRONOBU;BAJI TORU;NOGUCHI KOKI;AKAO YASUSHI;BABA SHIRO |
分类号 |
G06F9/30;G06F12/06;G06F9/34;G06F9/355;G06F9/38;G06F12/00;G06F13/16;G06F15/76;G06F15/78 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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