主权项 |
1. An integrated circuit comprising:
(A) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead; (B) a first test access port having a clock input connected to the first test clock lead and being free of the second test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the first test access port being free of any topology selection logic, and having class T0-T2 capabilities; and (C) a second test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port including topology selection logic, being coupled in a Star-4 branch, having no class T0-T2 capabilities, and having class T3, T4(W), and T5(W) capabilities. |