PHASE LOCKED LOOP FREQUENCY CALIBRATION CIRCUIT AND METHOD

摘要

A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.

主权项

1. A phase locked loop frequency calibration circuit, comprising a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator;
an output of the voltage controlled oscillator is connected with a first input of the frequency divider, an output of the frequency divider is connected with a first input of the counter, a second input of the frequency divider, a first input of the timer, and a second input of the counter are respectively connected with a first output of the control module, a third input of the counter is connected with an output of the timer, an output of the counter is connected with a first input of the control module, a reference clock signal is sent to a second input of the timer and a second input of the control module, respectively, a number of clocks used by the frequency divider to perform frequency division on an output clock signal of the voltage controlled oscillator is sent to a third input of the control module, an output capacitor array control word of a second output of the control module is sent to an input of the voltage controlled oscillator; the control module is configured to: clear the timer, the counter and the frequency divider, respectively, and control the counter to count an output clock signal of the frequency divider within a preset time, wherein the preset time is duration required for the timer to change from zero to overflow; obtain a count value A resulting from the counter counting the output clock signal of the frequency divider within the preset time; calculate output frequency of the voltage controlled oscillator according to the count value A, and compare the output frequency with an expected frequency; and if an absolute value of a difference between the output frequency and the expected frequency is greater than or equal to a preset difference value, then adjust a number of switched capacitors of the voltage controlled oscillator, so as to adjust the output frequency of the voltage controlled oscillator.