| 发明名称 |
CIRCUIT FOR DIGITIZING PHASE DIFFERENCES, PLL CIRCUIT AND METHOD FOR THE SAME |
| 摘要 |
A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed. |
| 申请公布号 |
US2016308541(A1) |
申请公布日期 |
2016.10.20 |
| 申请号 |
US201514690085 |
申请日期 |
2015.04.17 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
发明人 |
LIU CHIH-MIN;CHANG CHIN-HAO |
| 分类号 |
H03L7/099;H03L7/089 |
主分类号 |
H03L7/099 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A phase-locked loop (PLL) circuit, comprising:
a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. |
| 地址 |
HSINCHU TW |
