发明名称 Data processing device
摘要 A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder (1) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU (4) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit (3).
申请公布号 US7971037(B2) 申请公布日期 2011.06.28
申请号 US20090472193 申请日期 2009.05.26
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OHTANI SUGAKO;KONDO HIROYUKI
分类号 G06F7/00;G06F9/302;G06F9/00;G06F9/30;G06F9/32;G06F9/34;G06F17/10 主分类号 G06F7/00
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