DECODING TECHNIQUES FOR READ-ONLY MEMORY

摘要

A memory circuit and an operation method thereof are provided to enable individual switching devices to have selective conductivity between a word line and a selected bit line according to the enabling due to the word line. Each of a plurality of bit line structures(102) includes at least three bit lines. A plurality of word lines(110) crosses with the bit line structure at plural sites(112). A plurality of switching devices is located at the selected site and is connected between the selected bit line of the adjacent bit line structure and the adjacent word line, and has selective conductivity according to the enabling by the adjacent word line. A plurality of column sense logic units is related with each corresponding bit line structure. A first logic gate comprises a first input part connected to a first bit line in the corresponding bit line structure and a second input part connected to a second bit line in the corresponding bit line structure. A second logic gate comprises a first input part connected to a third bit line in the corresponding bit line structure and a second input part connected to a second bit line in the corresponding bit line structure.