发明名称 CAPACITOR BUILT-IN WAFER LEVEL PACKAGE AND ITS MANUFACTURING METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a wafer level package which can be manufactured at a low cost, has a large routing versatility of a rewiring layer, and has a built-in capacitor having a large capacitance; and to provide its manufacturing method. <P>SOLUTION: The capacitor built-in wafer level package is equipped with: a sheet-like capacitor 18 constituted of an anode 18A composed of a valve metallic material electrically connected to a power source electrode 19 of a semiconductor integrated circuit device formed on a wafer, an anodic oxide film 18C being a dielectric film of the capacitor formed on the surface of the anode 18A composed of the valve metallic material, and a cathode 18B electrically connected to a grounding electrode 20 of the semiconductor integrated circuit device, interposing the anodic oxide film between the anode 18A composed of the valve metallic material and the cathode 18B, and composed of a conductive polymer material; and the rewiring layer 16 which contains the sheet-like capacitor 18 and puts together every electric wiring on the wafer. Its manufacturing method is also provided. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008227266(A) 申请公布日期 2008.09.25
申请号 JP20070065138 申请日期 2007.03.14
申请人 FUJITSU LTD 发明人 SHIOGA KENJI;KURIHARA KAZUAKI
分类号 H01L23/12;H01L21/3205;H01L21/822;H01L23/52;H01L27/04 主分类号 H01L23/12
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