| 摘要 |
A data transfer apparatus (100) includes a processing unit (101), a memory bank array (4), and a memory controller (3). The processing unit (101) outputs a plurality of offset values and a base address. The memory bank array includes a plurality of memory banks (4). The memory controller (3) offsets the base address by the offset values to generate offset addresses, and reads data from the memory bank array (4) using the offset addresses. The memory controller receives the offset values and base address from the processing unit (101). |
