发明名称 Timer unit circuit having plurality of output modes and method of using the same
摘要 A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.
申请公布号 US9448581(B2) 申请公布日期 2016.09.20
申请号 US201414560960 申请日期 2014.12.04
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Takata Yasuhiro
分类号 G06F1/04;G06F1/06;G06F1/025;H03K7/08 主分类号 G06F1/04
代理机构 McGinn IP Law Group, PLLC 代理人 McGinn IP Law Group, PLLC
主权项 1. A timer unit having a first output mode and a second output mode, the timer unit comprising: a first register that stores a first value; a second register that stores a second value; a third register that stores a third value; a first counter that generates a first count signal based on the first value; a second counter that generates a second count signal based on the second value; a third counter that generates a third count signal based on the third value; and an output circuit that outputs a first output signal and a second output signal, wherein, when the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the first count signal and the second count signal, and outputs the second output signal having a pulse width determined by the first count signal and the third count signal, and wherein, when the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the first count signal, the second count signal, and the third count signal.
地址 Kawasaki-Shi, Kanagawa JP