发明名称 |
PREPARATION METHOD FOR POWER DIODE |
摘要 |
A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10). |
申请公布号 |
US2016308029(A1) |
申请公布日期 |
2016.10.20 |
申请号 |
US201414902294 |
申请日期 |
2014.09.12 |
申请人 |
CSMC Technologies Fab1 Co., Ltd. |
发明人 |
Zhong Shengrong;Wang Genyi;Deng Xiaoshe;Zhou Dongfei |
分类号 |
H01L29/66;H01L29/06;H01L21/311;H01L21/28;H01L29/167;H01L21/027;H01L21/265;H01L21/3213;H01L21/324;H01L21/768;H01L21/02;H01L21/266 |
主分类号 |
H01L29/66 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method of manufacturing a power diode, comprising the following steps:
providing a substrate comprising a front side and a back side opposite to the front side; and growing an N-type layer on the front side of the substrate, wherein the N-type layer comprises a first surface away from the substrate; forming a terminal guard ring on the first surface of the N-type layer; forming an oxide layer on the first surface of the N-type layer, and performing a driving-in to the terminal guard ring; performing photoetching by using an active region photomask and etching the oxide layer on an active region area, and forming a gate oxide layer on the first surface of the N-type layer on the active region area; depositing a polysilicon layer on the gate oxide layer; performing photoetching by using a polysilicon photomask, implanting P-type ions into the N-type layer by using a photoresist as a masking layer, and forming a P-type body region below the polysilicon layer via ion scattering; etching the polysilicon layer by using the photoresist as the masking layer, implanting N-type ions into the P-type body region below the etched area, and forming an N-type heavily doped region; performing gate oxide layer etching and then silicon etching by using the photoresist as the masking layer, implanting P-type ions below the etched area via ion implantation, and forming a P+ region; performing thermal annealing, activating the implanted impurities and removing the photoresist; and performing metallization processing on the first surface and the back side of the substrate. |
地址 |
Wuxi New District CN |