SEMICONDUCTOR PACKAGES INCLUDING INTERCONNECTION MEMBERS

摘要

A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.

主权项

1. A semiconductor package comprising:
a main substrate; a sub-substrate spaced apart from the main substrate by a gap; a semiconductor chip disposed on the main substrate; an interconnection member including twisted wires of a plurality of strands and connecting the semiconductor chip to the sub-substrate; a main molding member covering the semiconductor chip and the main substrate; a sub-molding member covering the sub-substrate; and a stress buffer layer disposed between the main molding member and the sub-molding member, filling the gap between the main substrate and the sub-substrate, and surrounding a portion of the interconnection member, wherein a top surface of the stress buffer layer, a top surface of the main molding member and a top surface of the sub-molding member being coplanar.