Speicherzellenanordnung und Verfahren zu deren Herstellung

摘要

Several mutually insulated memory cell lines arranged in a semiconductor substrate (21) include each a first doped region (D1') and a second doped region (D2') between which are arranged a gate dielectric (29, 32) which contains a material with charge carriers capturing points and several gate electrodes (WL1', WL2'). The distance between adjacent gate electrodes (WL1', WL2') is smaller than the dimensions of the gate electrodes (WL1', WL2'). Information is stored by introducing charge carriers into the gate dielectric (29, 32). The gate electrodes (WL1', WL2') are preferably produced by a spacer technique.