发明名称 Phase locked loop circuit, reproduction apparatus and phase locking method
摘要 The invention provides a phase locked loop circuit, a reproduction apparatus and a phase locking method by which a capture range and a lock range can be widened. Before a phase locked loop circuit is locked, an output clock of a voltage controlled oscillator is counted with reference to a reference clock of a quartz oscillator, and an error component between run length limited codes reproduced from a disk and the reference clock is extracted. Then, the PLL circuit is constructed based on a result of addition of the counted value of the output clock and the extracted error component. After the phase locked loop circuit is locked, a phase error of the output clock of the voltage controlled oscillator against the run length limited codes reproduced from the disk is detected, and the PLL circuit is constructed based on the detected phase error.
申请公布号 US6150888(A) 申请公布日期 2000.11.21
申请号 US19980193112 申请日期 1998.11.16
申请人 SONY CORPORATION 发明人 NAKAZAWA, TETSUJI
分类号 H03L7/08;G11B7/005;G11B19/247;G11B19/28;G11B20/14;H03L7/10;H03L7/113;(IPC1-7):H03L7/07 主分类号 H03L7/08
代理机构 代理人
主权项
地址