| 发明名称 |
Method of forming an integrated power device and structure |
| 摘要 |
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
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| 申请公布号 |
US2006220140(A1) |
申请公布日期 |
2006.10.05 |
| 申请号 |
US20050095135 |
申请日期 |
2005.04.01 |
| 申请人 |
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. |
发明人 |
ROBB FRANCINE Y.;ROBB STEPHAN P.;VENKATRAMAN PRASAD;HOSSAIN ZIA |
| 分类号 |
H01L29/423 |
主分类号 |
H01L29/423 |
| 代理机构 |
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代理人 |
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