发明名称 DUTY SIGNAL COMPENSATION APPARATUS AND METHOD THEREOF
摘要 Proposed are an apparatus and a method to compensate for a duty signal to compensate for signal I and signal Q having a duty cycle of 25% by measuring timing between the signal I and the signal Q when the timing is dislocated between the signal I and the signal Q. The proposed apparatus comprises: a signal input unit in which a first signal and a second signal are inputted, a signal control unit to control each timing between a first signal and a second signal based on the first control signal and the second control signal and to output a combined signal in which the first signal and the second signal are combined; a combined signal control unit to output a first logic operation signal and a second logic operation signal by logically operating a duty signal and the combined signal; a determination unit to output the first control signal and the second control signal when the timing is dislocated by determining whether the timing between the first signal and the second signal is dislocated and to apply a third control signal to control the timing of the combined signal to the combined signal control unit; and a signal output unit to output the first signal and the second control signal which are controlled to be matched with the timing between the first signal and the second signal in the signal control unit.
申请公布号 KR20160069163(A) 申请公布日期 2016.06.16
申请号 KR20140174751 申请日期 2014.12.08
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 LEE, SEUNG SIK;KIM, JAE YOUNG;NAM, HONG SOON;CHOI, SANG SUNG
分类号 H04L7/00 主分类号 H04L7/00
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