发明名称 Electrical connector between die pad and z-interconnect for stacked die assemblies
摘要 Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
申请公布号 US9508689(B2) 申请公布日期 2016.11.29
申请号 US201514871185 申请日期 2015.09.30
申请人 Invensas Corporation 发明人 Co Reynaldo;Leal Jeffrey S.;Pangrle Suzette K.;McGrath Scott;Melcher De Ann Eileen;Barrie Keith L.;Villavicencio Grant;Del Rosario Elmer M.;Bray John R.
分类号 H01L25/065;H01L23/31;H01L23/00;H01L21/683;H01L25/00;H01L21/78 主分类号 H01L25/065
代理机构 Lerner, David, Littenberg, Krumholz & Mentlik, LLP 代理人 Lerner, David, Littenberg, Krumholz & Mentlik, LLP
主权项 1. A method for forming a connector on a die pad at a wafer level of processing, comprising forming a channel defining an interconnect die edge of a first die of the wafer and an adjacent edge of a second die of the wafer, wherein the interconnect die edge of the first die, the edge of the second die, and the channel therebetween have longest dimensions extending in a first direction, and a width of the channel extends in a second direction from the interconnect die edge to the adjacent edge of the second die; forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edge, and the edge of the second die, the insulative material spanning an entire width of the channel; forming spots of a curable electrically conductive material over die pads and extending over an interconnect die edge above the channel; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots.
地址 San Jose CA US