发明名称 BIT SYNCHRONIZATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To determine an optimum clock phase required for reproducing data by more accurately discriminating the data change phase of input data by performing processing for replacing detected data change phases into one position when two data change phases are detected at one data change point. SOLUTION: A data change phase detection part 4 detects the data change phase of burst signal from the respective outputs of flipflop 3 triggered by phase clocks 1 to (n). When two data change phases are detected at one data change point in this detection, a data change phase conversion processing part 5 performs processing for replacing the detected data change phases into one position. The clock of phase closer to the data change phase of burst signal processed and discriminated by the conversion processing part 5 is selected out of the phase clocks from 1 to (n) and outputted to a regenerative clock output terminal 7 by a selector circuit 6. Thus, the accurate and optimum regenerative clock can be provided.
申请公布号 JPH10327136(A) 申请公布日期 1998.12.08
申请号 JP19970131824 申请日期 1997.05.22
申请人 MITSUBISHI ELECTRIC CORP 发明人 ASASHIBA NORIHIRO;OKUMA HIROSHI;MAKINO SHINYA
分类号 H04L7/02;H04L7/04 主分类号 H04L7/02
代理机构 代理人
主权项
地址