| 摘要 |
<p>PROBLEM TO BE SOLVED: To suppress the through-current between a voltage terminal and reverse logic signal line at the time of an address changeover during a read operation by providing a current route between the voltage terminal and the reverse logic signal line with a program switch which conducts at the time of a program mode and a switch for erase which conducts at the time of an erase mode and shutting off the both switch during a read mode. SOLUTION: A multiple input logic circuit X1 outputs a GND and supplies a Vcc to a Y gate selection line 8 via an inverter circuit 6 through the reverse logic signal line 2 at the time of selecting a Y gate 4. When, for example, the Y gate 4 is switched from non-selection to selection in the read mode, the output of the multiple input logic circuit X1 falls from the Vcc toward the GND and a feedback control switch M5 controlled via an inverter circuit consisting of MOS transistors(TRs) M6, M7 is delayed in shut-off. A PMOSTR M4 is disposed at this time to shut off the switch by a READ signal.</p> |
