| 摘要 |
<p>To restrain cycle-to-cycle jitter in a clock generator subjected to EMI measure, in a 2nd order PLL having a loop filter 7 including a first capacitor and a first resistor, a reduction in a comparison frequency is restrained by using a clock modulating circuit 2 controlled by a signal 16 provided by dividing an oscillation signal of a voltage control type oscillator 13 and recurrently controlling a divider 15, generation of high frequency noise is minimized by using a 1st order DELTA SIGMA modulator 21 in the clock modulation circuit 2 and the system is constituted by a 3rd order PLL by using a second capacitor 3 having a capacitance value of about 1/10 or more of that of the first capacitor in parallel with the loop filter 7 to thereby restrain the intercycle jitter by effectively removing the high frequency noise. <IMAGE></p> |
