SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE

摘要

Devices and methods to reduce parasitic capacitance are disclosed. A device includes a dielectric layer (114). The device includes first and second conductive structures (102, 104) and an etch stop layer (105) proximate to the dielectric layer. The etch stop layer defines first and second openings (109, 119) proximate to a region of the dielectric layer between the first and second conductive structures. The device includes first and second airgaps (107, 113) within the region. The device includes a layer of material (110) proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer covers the first and second airgaps.