INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE

摘要

A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.

主权项

1. A processor, comprising:
a Level-2 (L2) cache; a first cluster of execution units; a second cluster of execution units; a first data cache unit (DCU) communicatively coupled to the first cluster of execution units and to the L2 cache; and a second DCU communicatively coupled to the second cluster of execution units and to the L2 cache; wherein:
the first DCU and the second DCU each include:
a data cache;a first logic to receive a memory operation from an execution unit;a second logic to respond to the memory operation with information from the data cache when the information is available in the data cache; anda third logic to retrieve the information from the L2 cache when the information is unavailable in the data cache; andthe processor further comprises a fourth logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.