Multi-threaded GPU pipeline

摘要

Techniques are disclosed relating to a multithreaded execution pipeline. In some embodiments, an apparatus is configured to assign a number of threads to an execution pipeline that is an integer multiple of a minimum number of cycles that an execution unit is configured to use to generate an execution result from a given set of input operands. In one embodiment, the apparatus is configured to require strict ordering of the threads. In one embodiment, the apparatus is configured so that the same thread access (e.g., reads and writes) a register file in a given cycle. In one embodiment, the apparatus is configured so that the same thread does not write back an operand and a result to an operand cache in a given cycle.

主权项

1. An apparatus, comprising:
an execution pipeline that includes an execution unit configured to generate execution results from input operands, wherein, for any given set of input operands, the execution unit is configured to use at least N cycles after receiving input operands to generate a corresponding execution result, wherein N is an integer greater than or equal to 2; wherein the apparatus is configured to assign a number of threads M for execution by the execution pipeline, wherein M is an integer multiple of N; and wherein the apparatus is configured to strictly order execution of the threads by the execution pipeline, such that an input to a given stage within the execution pipeline is associated with a particular one of the threads once and only once every M cycles during strictly ordered execution of the threads.