发明名称 HORIZONTAL DEFLECTION OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a horizontal deflection output circuit by which the power loss of the entire circuit is reduced, even when a horizontal deflection frequency is high and the reduction effect of the power loss is enhanced stably even if environment such as the horizontal deflection frequency and ambient temperature or the like is changed. SOLUTION: A parallel circuit consisting of a bipolar transistor(TR) 6 and a damper diode 7 configure a 1st switch circuit and a parallel circuit consisting of a FET 14 and a damper diode 15 configure a 2nd switch circuit. Resonance capacitors 8, 9, 16 are connected to the 1st and 2nd switch circuits. A phase control circuit 18 gives a square wave pulse Vg to decide the on/off of the FET 14 to the FET 14. A rectifier circuit 19 and an operational amplifier 20 control the phase control circuit 18, so that a peak level of pulses produced between a drain and a source of the FET 14 is almost constant.
申请公布号 JPH1146308(A) 申请公布日期 1999.02.16
申请号 JP19970215864 申请日期 1997.07.25
申请人 VICTOR CO OF JAPAN LTD 发明人 KASHIWAGI SHIGERU
分类号 H04N3/16;(IPC1-7):H04N3/16 主分类号 H04N3/16
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