| 摘要 |
The present invention relates to a parity checking circuit, comprising: a first signal combination unit for generating a first to an N combination signals by combining at least one signal among the first to the N (wherein N is a natural number) signals, wherein a K (wherein K is a natural number and 2<=K<=N) combination signal among the first to the N combination signals is a signal which combines the first to the K signals among the first to the N signals; a parity checking unit for detecting an error in the first to the N signals by responding to the N combination signal; a second signal combination unit for generating a first to an N restoration signals by combining at least one signal among the first to the N combination signals, wherein a K restoration signal among the first to the N restoration signals is a signal which combines a (K-1) combination signal and the K combination signal among the first to the N combination signals; and a signal storage unit for storing the first to the N restoration signals if an error occurs according to a detection result of the parity checking unit. |
