发明名称 INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL
摘要 A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This continuous cooling channel may provide a path for a cooling source such as a fluid pumped from an external fluidic-cooling circulation driver to make physical contact locally with and cool the back end levels within the IC chip that may generate heat as a byproduct of the IC device's routine operations. Such a cooling structure is achieved by removing a horizontal portion of a barrier layer from an intermediate region of an interlevel interconnect structure, selective to a vertical portion of the barrier layer located on a sidewall of the interlevel interconnect structure, using gas cluster ion beam etching as well as removing the bulk conductor by additional means.
申请公布号 US2016254208(A1) 申请公布日期 2016.09.01
申请号 US201615158664 申请日期 2016.05.19
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Clevenger Lawrence A.;McGahay Vincent J.;Nag Joyeeta;Xu Yiheng
分类号 H01L23/367;H01L23/528;H01L23/522 主分类号 H01L23/367
代理机构 代理人
主权项 1. An integrated circuit chip having a continuous cooling channel extending through back end of the line (BEOL) of the chip comprising: a pair of vertical channel openings extending through two or more dielectric layers in the back end of line of the chip, wherein each vertical channel opening has a bottom and a top; a horizontal channel opening connecting the pair of vertical channel openings at their bottoms; and a barrier layer having a vertical portion on a sidewall of each of the vertical channel openings and a horizontal portion, wherein the horizontal portion of the barrier layer extends laterally into each of the vertical channel openings at a location where the dielectric layers meet, andwherein the horizontal portion extends only partially into the vertical channel opening such that a sidewall of the horizontal portion of the barrier layer is exposed; a pair of plugs at the top of the pair of vertical channel openings; and an electrical interconnect located adjacent to the channel opening, wherein the electrical interconnect includes one or more layers of a conductive material.
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