PARTIALLY RECESSED CHANNEL CORE TRANSISTORS IN REPLACEMENT GATE FLOW

摘要

An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

主权项

1. A method of forming an integrated circuit, comprising the steps of:
providing a substrate comprising semiconductor material; concurrently removing a first sacrificial gate in a first MOS transistor and removing a second sacrificial gate in a second MOS transistor; concurrently removing a first sacrificial gate dielectric layer in said first MOS transistor and removing a second sacrificial gate dielectric layer in said second MOS transistor; forming an etch mask over said substrate in said first MOS transistor so as to expose said substrate in said first MOS transistor; removing semiconductor material from said substrate in an area for a recessed replacement gate in said first MOS transistor, such that an etched surface of said substrate is substantially coplanar with an etched surface of field oxide adjacent to said etched surface of said substrate, and such that semiconductor material is not removed from said substrate in said second MOS transistor; concurrently forming a first replacement gate dielectric layer in said first MOS transistor and forming a second replacement gate dielectric layer in said second MOS transistor; and concurrently forming a recessed first replacement gate on said first replacement gate dielectric layer and forming a second replacement gate on said second replacement gate dielectric layer; so that said recessed first replacement gate is recessed below a top surface of said substrate and said first MOS transistor and said second MOS transistor have a same polarity.