发明名称 |
Solid-state image pickup device, image pickup system using solid-state image pickup device, and method of manufacturing solid-state image pickup device |
摘要 |
In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion. |
申请公布号 |
US9466627(B2) |
申请公布日期 |
2016.10.11 |
申请号 |
US201514957352 |
申请日期 |
2015.12.02 |
申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
Kato Aiko;Hashimoto Kouhei;Tamura Seiichi |
分类号 |
H01L27/146 |
主分类号 |
H01L27/146 |
代理机构 |
Canon USA, Inc. IP Division |
代理人 |
Canon USA, Inc. IP Division |
主权项 |
1. A solid-state image pickup device comprising:
a first transfer transistor configured to transfer carriers stored at a first semiconductor region of a first conductive type disposed in a semiconductor substrate to a second semiconductor region of the first conductive type disposed in the semiconductor substrate; a second transfer transistor configured to transfer the carriers held at the second semiconductor region to a third semiconductor region of the first conductive type disposed in the semiconductor substrate; an amplification transistor configured to output a signal based on a potential of the third semiconductor region; a first insulating film disposed over the first transfer transistor and the second transfer transistor; and a light shielding film configured to overlap an edge of a gate electrode of the first transfer resistor on a first semiconductor region side and an edge of the gate electrode on a second semiconductor region side in planar view, wherein the light shielding film has:
a first bottom surface located above an upper surface of the gate electrode and below an upper surface of the first insulating film;a second bottom surface located above the first semiconductor region and at a position closer to a surface of the semiconductor substrate than the first bottom surface; anda third bottom surface located above the second semiconductor region and at the position closer to the surface of the semiconductor substrate than the first bottom surface. |
地址 |
Tokyo JP |