发明名称 |
Semiconductor integrated circuit and method of producing the same |
摘要 |
Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate. |
申请公布号 |
US9466607(B2) |
申请公布日期 |
2016.10.11 |
申请号 |
US201514880690 |
申请日期 |
2015.10.12 |
申请人 |
TOHOKU UNIVERSITY |
发明人 |
Endoh Tetsuo;Moon-Sik Seo |
分类号 |
H01L31/119;H01L27/115;G11C16/04;H01L29/788;H01L27/088;H01L29/66;H01L29/423 |
主分类号 |
H01L31/119 |
代理机构 |
Westerman, Hattori, Daniels & Adrian, LLP |
代理人 |
Westerman, Hattori, Daniels & Adrian, LLP |
主权项 |
1. A method of producing a semiconductor integrated circuit, comprising:
a step of layering three types of different layers on a substrate; a step of forming an opening up to the surface of the substrate; a step of etching a region functioning as a floating gate in the layers layered adjacent to the opening; a step of depositing a semiconductor material in the opening including the region functioning as the floating gate; a step of subjecting a region including the deposited semiconductor material to an anisotropic etching to form an opening in a region in which a semiconductor pillar and a tunnel insulating layer are to be formed and to form the floating gate; a step of depositing a tunnel insulating layer on a side wall of the opening formed by the anisotropic etching; a step of depositing a semiconductor material on the opening surrounded by the tunnel insulating layer to form the semiconductor pillar; a step of etching the three types of different layers having etching selectivity to one another except for a layer including the floating gate and a layer functioning as a separation layer between cells; a step of forming another insulating layer on the floating gate, the layer functioning as the separation layer, and the tunnel insulating layer; a step of depositing, on the another insulating layer, a material to be used for a control gate; and a step of etching the material to be used for the control gate so as to form the control gate and a word line. |
地址 |
Sendai-shi JP |