| 摘要 |
The present invention is generally directed to the transmission of data in various types of communication systems, including local area networks (LANs) and wide area networks (WANs). A main object of the present invention is to provide a system (2) based on a parallel structure that can assemble (3) and disassemble (4) packet information (1) in constant time, no matter how corrupted, out of order, duplicated the arriving packets (1a, 1b). A further object of the present invention is to provide a system (2) that would improve efficiency in broadband networks, particularly if implemented in a VLSI chip using the low complexity architecture-and-reassembly of the present invention.
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