Method to manage current during clock frequency changes

摘要

A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

主权项

1. A system, comprising:
a clock generator configured to generate a clock signal, wherein a frequency of the clock signal has an initial frequency value; a clock divider coupled to the clock generator, wherein the clock divider is configured to divide the frequency of the clock signal by a divisor value; a processor coupled to the clock divider, wherein the processor is configured to select a new frequency value for the clock signal; and a clock management unit, configured to:
increase the divisor value in response to the processor selecting the new frequency value;adjust the frequency of the clock signal to the new frequency value selected by the processor; andadjust the divisor value in a series of adjustments in response to a determination that the frequency of the clock signal has stabilized at the new frequency value, wherein at least a predetermined time period elapses between each adjustment of the series of adjustments.