发明名称 |
A content addressable memory (CAM) architecture providing improved speed |
摘要 |
<p>This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match. <IMAGE></p> |
申请公布号 |
EP1460640(A2) |
申请公布日期 |
2004.09.22 |
申请号 |
EP20040006654 |
申请日期 |
2004.03.19 |
申请人 |
STMICROELECTRONICS PVT. LTD |
发明人 |
SRIVASTAVAAN, RAJEEV;GROVER, CHIRANJEEV |
分类号 |
G11C15/00;G11C15/04;(IPC1-7):G11C15/04 |
主分类号 |
G11C15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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