Methods and Systems for Chip-to-Chip Communication with Reduced Simultaneous Switching Noise

摘要

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

主权项

1. An apparatus comprising:
an encoder configured to encode the binary data to a vector signaling code word as transitions from a previously transmitted vector signaling code word of three or more levels in the transmission interface, wherein the encoder is configured to check one or more bits for a condition that if satisfied, transitions a single element of the previously transmitted vector signaling code word according to a first transition-limiting function, and if the condition fails, transitions two or more elements of the previously transmitted vector signaling code word according to a second transition-limiting function; and an output driver circuit configured to provide the vector signaling codeword in one transmission interval on a multi-wire bus.