发明名称 System in package with built-in test-facilitating circuit
摘要 This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.
申请公布号 US8040148(B2) 申请公布日期 2011.10.18
申请号 US20080092238 申请日期 2008.04.30
申请人 TAIYO YUDEN CO., LTD. 发明人 SATOH MASAYUKI
分类号 G01R31/02;H01L21/48;H01L23/498 主分类号 G01R31/02
代理机构 代理人
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