| 摘要 |
In a preferred embodiment of the present invention, first MOS transistors (21) connected to first source electrodes (11) and second MOS transistors (22) connected to second source electrodes (12) are arranged alternately next to each other on one chip. Different potentials are applied respectively to the first source electrodes (11) and to the second source electrodes (12), and both of the MOS transistors (21, 22) are controlled with respect to an ON or Off state by one gate terminal. Currents flow along surroundings of trenches (4), whereby on-resistance is reduced. |
