TECHNOLOGIES FOR IMPROVED HYBRID SLEEP POWER MANAGEMENT

摘要

Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware environment, the computing device reserves a memory block for firmware use and copies platform wake code to a secure memory location, such as system management RAM (SMRAM). At runtime, an operating system may execute with the processor in protected mode. In response to a request to enter a sleep or suspend state, the computing device generates a system management interrupt (SMI). In an SMI handler, the computing device copies the wake code from SMRAM to the reserved memory block. The computing device resumes from the SMI handler to the wake code with the processor in real mode. The wake code enters the low-power idle state and then jumps to a wake vector of the operating system after receiving a wake event. Other embodiments are described and claimed.

主权项

1. A computing device for hybrid sleep power management, the computing device comprising:
a security module to: (i) reserve, during a pre-boot firmware environment of the computing device, a reserved memory block and (ii) store, during the pre-boot firmware environment, a wake routine in a secure memory location that is not accessible by an operating system of the computing device; a system management module to: (i) copy, by a system management interrupt handler of the computing device, the wake routine from the secure memory location to the reserved memory block in response to a request to enter a sleep power management mode generated by the operating system in a first processor mode; and (ii) resume, by the system management interrupt handler, execution of the computing device in a second processor mode starting at the wake routine stored in the reserved memory block; and a wake code module to enter, by the wake routine of the computing device, a low-power idle state in response to resumption of execution in the second processor mode.