SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION

摘要

Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

主权项

1. A memory integrated circuit chip configured to communicate with a memory device controller, the memory integrated circuit chip comprising:
a command receiving module configured to receive a command from the memory device controller; a command execution module configured to execute the command received; and an indicator module configured to store an address and an associated indicator in the memory integrated circuit chip, the indicator indicative of execution of the command by the memory integrated circuit chip at the address.