发明名称 Method of wiring semiconductor integrated circuit and semiconductor integrated circuit
摘要 In designing wiring for semiconductor integrated circuits, wiring channels are assigned to reduce a signal delay time developed parallel traces. The selection of the wiring channels for all of the wiring oriented nets of the circuits is based on the trunk trace length between the terminals. For the longer trunk trace lengths, a double-pitch wiring channel is assigned. First, the determined trunk-trace lengths are sorted in decreasing order of length. Then, a double-pitch wiring channel is assigned for the trunk-trace lengths that are greater than a predetermined length. When no double pitch channels remain, single pitch channels are used.
申请公布号 US5872719(A) 申请公布日期 1999.02.16
申请号 US19960691708 申请日期 1996.08.02
申请人 HITACHI, LTD. 发明人 MIYAZAKI, YOSHIAKI;SUZUKI, KATSUYOSHI;KATO, NAOKI;YAMADA, HIROMITSU
分类号 H05K3/00;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 H05K3/00
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