发明名称 Method of manufacturing interconnect substrate
摘要 A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method including: (a) forming a plurality of rows of linear catalyst layers on a substrate; and (b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers, at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.
申请公布号 US2007218192(A1) 申请公布日期 2007.09.20
申请号 US20070716738 申请日期 2007.03.09
申请人 SEIKO EPSON CORPORATION 发明人 KIMURA SATOSHI;FURIHATA HIDEMICHI;KANEDA TOSHIHIKO
分类号 B05D5/12;B28B19/00 主分类号 B05D5/12
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