MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS

摘要

In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

主权项

1. Apparatus comprising:
first and second data paths on one of which data is transferred for read memory operations and on the other of which data is transferred for write memory operations; a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal; a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal; and a cross coupler capable of coupling one of the first clock output and the second clock output to either the first data path or the second data path during a first memory operation and coupling the other of the first clock output and the second clock output to either the first data path or the second data path during a second memory operation following the first memory operation.