LOW POWER LOW-DENSITY PARITY-CHECK DECODING

摘要

In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

主权项

1. An apparatus configured to evaluate a set of values organized based on a set of bit positions, each of the values including a respective set of bits associated with the respective bit positions, the apparatus comprising:
a set of modules associated with the respective bit positions, the set of modules configured to determine, based on a set of bitwise comparisons performed for the respective bit positions based on the bits of the values associated with the respective bit positions, a magnitude of a minimum value of the set of values; wherein, for each of the modules associated with the respective bit positions, the respective module includes a respective bit detector module configured to receive a respective set of input bits for the respective bit position and configured to generate a respective output bit indicative as to whether at least one of the input bits for the respective bit position is a first bit value; wherein, for each of a subset of the modules associated with the respective bit positions, the respective module includes a respective mask generation module configured to generate, based on the respective set of bits associated with the respective bit position and based on the respective output bit generated by the respective bit detector module for the respective bit position, a respective disable signal comprising a respective set of disable bits associated with the respective values of the set of values, wherein, based on the respective output bit generated by the respective bit detector module for the respective bit position being indicative that at least one of the input bits for the respective bit position is the first bit value, each of the disable bits associated with a respective one of the values for which the bit in the respective bit position of the value is a second bit value and the bit in a next bit position of the value is the first bit value is configured to change the bit in the next bit position of the value from the first bit value to the second bit value for processing by the bit detector module associated with the next bit position.