| 发明名称 |
FREQUENCY DIVIDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT |
| 摘要 |
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits. |
| 申请公布号 |
US2016233867(A1) |
申请公布日期 |
2016.08.11 |
| 申请号 |
US201615132824 |
申请日期 |
2016.04.19 |
| 申请人 |
SOCIONEXT INC. |
发明人 |
TAMURA Tetsuro |
| 分类号 |
H03K23/52;H03M9/00;H03K21/02;H03K3/037;H03K19/21 |
主分类号 |
H03K23/52 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A frequency dividing circuit comprising:
a plurality of latch circuits that are connected in series in a loop in which the latch circuit driven at rising of a clock signal and the latch circuit driven at falling of the clock signal are alternately connected; and a generation circuit configured to generate a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of the plurality of latch circuits. |
| 地址 |
Yokohama-shi JP |
