发明名称 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
摘要 To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.
申请公布号 US2016233865(A1) 申请公布日期 2016.08.11
申请号 US201615014081 申请日期 2016.02.03
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 TAMURA Hikaru;TSUTSUI Naoaki;ISOBE Atsuo
分类号 H03K19/00;H01L23/528;H01L27/12;H01L29/786;H01L27/06;H01L27/02;H01L23/532 主分类号 H03K19/00
代理机构 代理人
主权项 1. A semiconductor device including a plurality of logic cells, the semiconductor device comprising: a first element layer; a second element layer; and first to k-th wiring layers (k is an integer of greater than 3), wherein each of the first element layer and the second element layer is provided with a plurality of transistors, wherein the first to k-th wiring layers are stacked in this order, wherein the first element layer is provided under the first wiring layer, wherein the second element layer is provided between the second wiring layer and the third wiring layer, wherein the transistors of the logic cells are provided in the first element layer, wherein wirings of the logic cells are provided in the first wiring layer or the second wiring layer, and wherein an input port and an output port of the logic cell are provided in the third wiring layer.
地址 Atsugi-shi JP