Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling

摘要

Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

主权项

1. A successive-approximation register (SAR) based analog-to-digital converter (ADC) circuit comprising:
a comparator comprising a first input for receiving an input voltage signal and a second input for receiving a signal representing a reference voltage signal, the comparator configured to generate a comparator output signal representing a difference between the input voltage signal and the reference signal during a first comparison cycle; a control logic comprising a first input coupled to the comparator to receive the comparator output signal and a second input for receiving a clock signal, the control logic configured to generate a control output signal representing the comparator output signal at a latching time defined by a switching of the clock signal; and a digital-to-analog converter (DAC) capacitor array coupled to the comparator, the DAC capacitor array configured to receive the comparator output signal from the comparator before the latching time to generate an approximation of the input voltage signal.