FREQUENCY DIVISION CIRCUIT, METHOD OF CONTROLLING FREQUENCY DIVISION CIRCUIT, AND ANALOG ELECTRONIC TIMEPIECE

摘要

A frequency division circuit includes a first frequency division circuit which divides a frequency of a reference signal that is generated by an oscillation circuit; an input and output terminal from which an output signal of the first frequency division circuit is output to the outside; a selection circuit which outputs one of a first intermediate signal that is one of a signal which is output to the input and output terminal and a signal which is input from the input and output terminal, and a second intermediate signal that is an output signal of the first frequency division circuit, as an intermediate signal; a second frequency division circuit which divides a frequency of the intermediate signal; and a switching time count circuit which counts a predetermined amount of time after startup of the frequency division circuit, and switches the intermediate signal that is output from the selection circuit from the first intermediate signal to the second intermediate signal, after the predetermined amount of time passes.

主权项

1. A frequency division circuit comprising:
a first frequency division circuit which divides a frequency of a reference signal that is generated by an oscillation circuit; an input and output terminal from which an output signal of the first frequency division circuit is output to the outside; a selection circuit which outputs one of a first intermediate signal that is one of a signal which is output to the input and output terminal and a signal which is input from the input and output terminal, and a second intermediate signal that is an output signal of the first frequency division circuit, as an intermediate signal; a second frequency division circuit which divides a frequency of the intermediate signal; and a switching time count circuit which counts a predetermined amount of time after startup of the frequency division circuit, and switches the intermediate signal that is output from the selection circuit from the first intermediate signal to the second intermediate signal, after the predetermined amount of time passes.