发明名称 |
Memory system and management method thereof |
摘要 |
According to one embodiment, a memory system comprises a first nonvolatile semiconductor memory, a temperature sensor and a controller. The first nonvolatile semiconductor memory includes the first and second semiconductor chips. The temperature sensor detects a temperature of the first nonvolatile semiconductor memory. The controller acquires the wear level per block of the first and second semiconductor chips based on the temperature of the first nonvolatile semiconductor memory and the frequency of use of the first nonvolatile semiconductor memory, and sets, based on the wear level, an examination frequency for defining a cycle of examination of quality of data per block of the first and second semiconductor chips. |
申请公布号 |
US9362000(B2) |
申请公布日期 |
2016.06.07 |
申请号 |
US201414579127 |
申请日期 |
2014.12.22 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Takizawa Kazutaka;Niijima Masaaki |
分类号 |
G11C16/04;G11C16/34 |
主分类号 |
G11C16/04 |
代理机构 |
White & Case LLP |
代理人 |
White & Case LLP |
主权项 |
1. A memory system comprising:
a first nonvolatile semiconductor memory including first and second semiconductor chips; a temperature sensor configured to detect a temperature of the first nonvolatile semiconductor memory; and a controller configured to control an operation of the first nonvolatile semiconductor memory, wherein the controller acquires a wear level per block of the first and second semiconductor chips based on the temperature of the first nonvolatile semiconductor memory and a frequency of use of the first nonvolatile semiconductor memory, and sets, based on the wear level, an examination frequency for defining a cycle of examination of quality of data per block of the first and second semiconductor chips. |
地址 |
Tokyo JP |